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Por favor, use este identificador para citar o enlazar este ítem: https://hdl.handle.net/20.500.12008/53698 Cómo citar
Título: A new level-set analysis and sparse storage format for the SPTRSV in GPUs
Autor: Freire, Manuel
Dufrechou, Ernesto
Ezzatti, Pablo
Tipo: Preprint
Palabras clave: Sparse triangular linear systems, GPU, Level-set analysis, Synchronization-free methods
Fecha de publicación: 2024
Resumen: Due to its relevant role in many numerical methods, the solution of sparse triangular linear systems (SpTRSV) in parallel platforms is continuously studied to extract as much performance as possible from the latest hardware architectures. In the case of GPUs, the latest solvers use the synchronization-free paradigm. When the problem involves several system solutions for the same matrix, they often pre-process it through a levelset analysis to improve the equation solution scheduling in the solution phase. In addition, other optimizations address the load balancing issues and irregular memory access of the SpTRSV. In this work, we modify the classical approach to compute the level sets used in the parallel SpTRSV computation, and we show that the new strategy generally reduces the computation time of the solver. Furthermore, we design an internal matrix representation that can significantly accelerate the solution stage at the cost of increasing the memory storage requirements of the algorithm. The experimental evaluation shows that the proposed modifications can improve the performance of a recent levelset and synchronization-free solver by up to 70%, significantly outperforming other state-of-the-art solvers, especially when several linear systems must be solved for each analysis phase.
Financiadores: FCE_3_2022_1_172419 - MODELAR: Modelado del desempeñO de métoDos numÉricos en pLataformas de hArdware heteRogéneas.
Citación: Freire, M., Dufrechou, E. y Ezzatti, P. A new level-set analysis and sparse storage format for the SPTRSV in GPUs [Preprint] Publicado en : 2024 IEEE 36th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Hilo, HI, USA, 2024, pp. 59-69, DOI: 10.1109/SBAC-PAD63648.2024.00014.
Licencia: Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0)
Aparece en las colecciones: Publicaciones académicas y científicas - Instituto de Computación

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