Design method for an ultra low power, low offset, symmetric OTA

Abstract

A design method for ultra low power, low offset, symmetric OTAs is presented. The method is based on the gm/ID methodology and uses a model of MOS transistor valid in all the regions of operation which assures that the optimal operating point is chosen. The method was used to design a 2.5 μA/V-cascoded OTA with minimum offset and current consumption in a 0.5 μm CMOS technology. Post layout Montecarlo simulations were performed to obtain an estimated offset of the circuit. The standard deviation obtained from the Montecarlo simulation was 3.94 mV while that expected from the design method was 3.86 mV. The total current consumption of the OTA is only 400 nA. Simulation results confirm the reliability of the presented design method.