Variability-aware design method for a constant inversion level bias current generator

Abstract

A model for estimating the dispersion in the output of a MOS-only, constant inversion level, current reference is presented. Based on such model, a design method is introduced that allows to optimize how area is spent in order to minimize the dispersion for a given layout complexity. The model was successfully compared with the measurements of a current source fabricated on a 130-nm CMOS technology and with the simulations of six other designs. The fabricated, ultralow power, current source has an area of 0.032 mm 2 and produces 11.4 nA on average, while all eight measured devices were inside ±2.1% of the average.