Capacitances in compact 7-Parameter model for analog design in nanoscale process

Abstract

Lately efforts have been made to have compact models for nanoscale processes with a small number of parameters. These models consider one to four extra parameters in addition to the three basic parameters of the long-channel transistor compact models, which are the slope factor, the equilibrium threshold voltage and the normalization current. An acceptable accuracy of the dc characteristics and the small-signal parameters is obtained through these models. This work analyzes whether it is possible to obtain an adequate model of the intrinsic part of the capacitances by means of these models and parameters, while proposing a simple method to account for the extrinsic part of the capacitances. The proposed method, together with the model, is tested for minimum-length transistors in an FD-SOI 28 nm process and applied to the design of a low-voltage LC oscillator. The results obtained by these means are compared with the results of a look-up table approach and with simulation results, showing a reasonable agreement.