Design of DC/DC switched capacitor monolithic converter for ultra low power

Abstract

Integrated DC-DC switched capacitor converters are a subgroup of DC-DC converters that utilize only switches and capacitors to realize the desired voltage conversion. Unlike inductor-based converters that store energy by way of a magnetic field, the energy in a switched capacitor converter is stored by means of an electric field between the capacitor plates. Not utilizing inductors makes them ideal for integrated circuits Power Management, given that the use of inductors is inconvenient in integrated circuits [1]. Switched capacitor converters have been used historically to obtain the necessary voltage for programming FLASH type memories [2], voltages for the RS232 communication standard, and also powering LED-based lighting systems. More recently interest in fully integrated System on Chip(SoC) and reduction in the final size of products have popularized the use of these converters. A cellphone system has multiple continuous voltage domains that feed different parts of the system, all powered by only a battery whose voltage varies with its charge. The rise in number of transistors per unit-area of silicon has come with rising power dissipation, which must be managed. Combined with high power demand from the battery by laptops and cellphones or the Ultra Low Power(ULP) devices for Internet of things(IoT) or Active Implantable Medical Devices(AIMDs) has stimulated the use of Dynamic Power Management techniques like Dynamic Voltage Scaling(DVS) directed to satisfying all power demands of a fully integrated system in a tight budget. All of this has created an area of research in Power Management where DC-DC switched capacitor converters play a significant role. This work is focused on the development of a monolithic switched-capacitor converter in a CMOS SOI technology of 1.8V. It consists in the design of a limited-energy system Switched-Capacitor DC-DC Converter working in SSL(Slow Switching Limit), powered by a battery and oriented to the ULP. The three main points of this work are the following, first to build a multi-phased architecture converter, which helps to reduce output ripple. Second, that power consumption is proportional to the switching frequency even for very low power delivered to the load. This enables the converter to maintain high efficiency for low output power loads. And lastly, to have a fast response to a load current step, this is important as the majority of loads will be digital circuits that consume a high current for a short time at the clock edge, this enables the system to reduce the size of the output filtering capacitor, facilitating the full integration of the system. Furthermore, a novel optimization strategy was developed in order to determine the sizing of the converter components. The only other work done on the subject is [3], as far as the author is aware. This work is more general in the sense that it applies to all converter topologies, but it assumes the converter always operates in the intersection between SSL and FSL, because this point is optimum for a desired load and efficiency. It does not consider a varying load, where the converter should be able to work in a range of different loads and frequencies. This works intends to solve the problem of optimum sizing so that the converter can operate successfully in a range of conditions and always satisfy its constrains.