Is intrinsic noise a limiting factor for subthreshold digital logic in nanoscale CMOS?

Abstract

Intrinsic noise has been predicted as a limit to CMOS scaling. If this is the case, the effect would be more severe at low supply voltages, such as the ones applied in subthreshold digital circuits. In this work the effect of intrinsic noise in subthreshold digital nanoscale CMOS is analysed for the first time. Key issues such as variability and the actual bandwidth of the studied circuits are taken into account. Most of previous works overestimate the impact of intrinsic noise due to the use of simplified models of the MOS transistor. BSIM4 transistor model and PTM model files are used in order to correctly calculate noise RMS voltage at the output node of an inverter, which has not been done before in the subthreshold region. Technology scaling impact is explored by simulating technology nodes from 130 nm down to 16 nm and considering variability down to 32 nm. Simulation results show that variability strongly increases the minimum operating voltage of subthreshold digital nanoscale CMOS and thus making intrinsic noise not a problem, at least down to 32 nm, since commutation voltage maintains high enough to achieve negligible failure rates.