Bias circuit design for low-voltage cascode transistors

Abstract

This article presents a design methodology for the most simple cascode transistor's bias circuit, i.e. a diode-connected transistor, valid from weak to strong inversion. By taking advantage of a compact MOS transistor model, we show how the circuit can be easily designed to precisely fix the drain voltage of the cascoded transistor just above its saturation voltage. Test circuits were manufactured in a 0.35μm CMOS technology in order to test the design methodology under different operation regions (weak, moderate and strong inversion) and for long and short channel transistors. Standard deviation in measured drain voltage of the cascoded transistor is below 3% of its mean.