Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies

Abstract

An LC-VCO design optimization, based on the gm/ID methodology, is presented throughout this work, highlighting how, by applying all regions of inversion of the MOS transistor, the trade-off between phase noise and current consumption can be optimized for the application. Both transistor compact model equations and transistor data acquired from simulation are used to obtain gm/ID curves as well as normalized capacitances. Influence of tank elements’ characteristics in the VCO performance is also discussed. Results of applying the methodology in the design of two VCOs in 0.35μm and 90nm CMOS processes are described. Measurement results for the 915MHz VCO designed in 0.35μm CMOS technology are also presented, obtaining a current consumption of 3mA with a phase noise (L) of −107dBc/Hz @1MHz. The 2.4GHz VCO designed in a 90nm radiofrequency technology shows a current consumption of 400μA with a L of −111.4dBc/Hz @600kHz.