An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs

Abstract

Reducing the cost of test (in particular by reducing its duration and the cost of the required ATE) is a common goal which has largely been pursued in the past, mainly by introducing suitable on chip Design for Testability (DfT) circuitry. Today, the increasing popularity of sophisticated DfT architectures and the parallel emergence of new ATE families allow the identification of innovative solutions effectively facing that goal. In this paper we face the increasingly common situation of SoCs adopting the IEEE 1149.1 and 1500 standards for the test of the internal cores, and explore the idea of storing the test program on the tester in a compressed form, and decompressing it on-the-fly during test application. This paper proposes an improved version of an data compression/decompression technique which is well suited for reducing the size of test programs stored on the tester; this technique is particularly effective for very long sequential test vectors generated to test SoCs by means of low-cost test procedures; thus, the paper outlines the characteristics of an FPGA-based low-cost tester platform that takes advantage of the described compression schema. The effectiveness of the proposed methodology was demonstrated by practically testing some SoCs equipped with suitable DfT for supporting low-cost testing resorting to a low-cost tester implementing the proposed architecture and the compression/decompression technique.