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Issue Date
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2017
Optimum nMOS/pMOS imbalance for energy efficient digital circuits
Veirano Núñez, Francisco
;
Naviner, Lirida
;
Silveira, Fernando
2015
Is intrinsic noise a limiting factor for subthreshold digital logic in nanoscale CMOS?
Veirano Núñez, Francisco
;
Silveira, Fernando
;
Naviner, Lirida
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Naviner, Lirida
2
Veirano Núñez, Francisco
Keywords
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Asymmetric length biasing
1
CMOS integrated circuits
1
Digital circuits
1
Leakage currents
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Low energy
1
Mathematical model
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