Modeling a nanometer FD-SOI transistor with a basic all-region MOSFET model

Abstract

The suitability of a basic, long channel, compact, bulk transistor model coupled with look-up-tables (LUTs) for application to a 28 nm FD-SOI technology is evaluated through simulations. The parameters comprising the LUTs are extracted as a function of the channel length and back-plane voltage, with very simple standard procedures intended for long channel transistors. The resulting model proved to be a simple, but very accurate way to describe the gm/I D curve in the moderate and weak inversion regions, with a straightforward analytical expression, even for minimum length transistors. This approach coupled with a LUT approach for the ID/ gds ratio, provides the main small signal model for design. It was also confirmed that reasonably accurate modeling of the intrinsic capacitances require a more complete modeling of the device.