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Title: | MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design |
Authors: | Flandre, Denis Serrano Gotarredona, T Linares-Barranco, B Silveira, Fernando Vancaillie, L |
Type: | Artículo |
Keywords: | MOSFET circuits, Analog design, Mismatch measurements |
Descriptors: | ELECTRÓNICA |
Issue Date: | 2003 |
Abstract: | Based on mismatch measurements performed on very different CMOS technologies and large operating temperature range, we propose to model more adequately the mismatch in weak and moderate inversion by adding a new term related to the mismatch of the body effect factor dependence on the gate voltage. The model is introduced in a top-down analog design methodology, applied to the current mirror case, revealing some nonobvious design rules as well as typical misconceptions. |
Description: | Postprint Trabajo presentado en ESSCIRC 2004. 29th European Solid-State Circuits Conference, Estoril, Portugal, 2003 |
Publisher: | ESSCIRC |
Citation: | Flandre, D, Serrano Gotarredona, T., Linares-Barranco, B., Silveira, F, Vancaillie, L. MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design [en línea] ESSCIRC 2004. 29th European Solid-State Circuits Conference, Estoril, Portugal, 2003 |
Academic department: | Electrónica |
Investigation group: | Microelectrónica |
License: | Licencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC - By-NC-ND) |
Appears in Collections: | Publicaciones académicas y científicas - Instituto de Ingeniería Eléctrica |
Files in This Item:
File | Description | Size | Format | ||
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VSLSF03.pdf | 113,9 kB | Adobe PDF | View/Open |
This item is licensed under a Creative Commons License