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Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.12008/20760 How to cite
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dc.contributor.authorde la Vega, Roberto Jes
dc.contributor.authorPérez Acle, Julioes
dc.contributor.authorFonseca de Oliveira, Andrées
dc.contributor.authorOliver, Juan Pabloes
dc.contributor.authorCanetti, Rafaeles
dc.date.accessioned2019-05-29T15:28:09Z-
dc.date.available2019-05-29T15:28:09Z-
dc.date.issued1998es
dc.date.submitted20190528es
dc.identifier.citationde la Vega, R.J., Pérez Acle, J. Fonseca de Oliveira, A, Oliver, J.P, Canetti, R. Implementation of adaptive logic networks on an FPGA board. Publicado en: Proceedings of SPIE 3526. Configurable Computing: Technology and Applications, Boston, MA, United States8 October 1998, https://doi.org/10.1117/12.327045es
dc.identifier.urihttps://hdl.handle.net/20.500.12008/20760-
dc.description.abstractThis work is part of a project that studies the implementation of neural network algorithms in reconfigurable hardware as a way to obtain a high performance neural processor. The results for Adaptive Logic Network (ALN) type binary networks with and without learning in hardware are presented. The designs were made on a hardware platform consisting of a PC compatible as the host computer and an ALTERA RIPP10 reconfigurable board with nine FLEX8K FPGAs and 512KB RAM. The different designs were run on the same hardware platform, taking advantage of its configurability. A software tool was developed to automatically convert the ALN network description resulting from the training process with the ATREE 2.7 for Windows software package into a hardware description file. This approach enables the easy generation of the hardware necessary to evaluate the very large combinatorial functions that results in an ALN. In an on-board learning version, an ALN basic node was designed optimizing it in the amount of cells per node used. Several nodes connected in a binary tree structure for each output bit, together with a control block, form the ALN network. The total amount of logic available on-board in the used platform limits the maximum size of the networks from a small to medium range. The performance was studied in pattern recognition applications. The results are compared with the software simulation of ALN networks.es
dc.languageenes
dc.rightsLas obras depositadas en el Repositorio se rigen por la Ordenanza de los Derechos de la Propiedad Intelectual de la Universidad De La República. (Res. Nº 91 de C.D.C. de 8/III/1994 – D.O. 7/IV/1994) y por la Ordenanza del Repositorio Abierto de la Universidad de la República (Res. Nº 16 de C.D.C. de 07/10/2014)es
dc.subject.otherSISTEMAS y CONTROLes
dc.titleImplementation of adaptive logic networks on an FPGA boardes
dc.typeArtículoes
dc.rights.licenceLicencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC - By-NC-ND)es
Appears in Collections:Publicaciones académicas y cientìficas - Instituto de Ingeniería Eléctrica

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