LC-VCO Design Optimization Methodology Based on the gm/ID Ratio for Nanometer CMOS Technologies

Abstract

In this paper, an LC-VCO design optimization methodology based on the gm/ID technique and on the exploration of all inversion regions of the MOS transistor is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semi-empirical models of MOS transistors and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design trade-offs are easily identified. Four LC-VCO designs in different inversion regions in a 90 nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4 GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2V power supply and presents a phase noise of −106.2 dBc/Hz at 400 kHz from the carrier.