Por favor, use este identificador para citar o enlazar este ítem: https://hdl.handle.net/20.500.12008/42722

Título:

TFET-Based Circuit Design Using the Transconductance Generation Efficiency gm/Id Method

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Autor:

Barboni, Leonardo
Siniscalchi, Mariana
Sensale Rodríguez, Berardi

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Tipo de documento:

Artículo

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Palabras clave:

Si-FinFETs
Tunnel field effect transistors (TFET)
Ultra-low power design
gm/Id method
One-stage common-source amplifier
Two-stage operational transconductance amplifier (OTA) with Miller effect compensation

Descriptores:

Electrónica

Año de publicación:

2015

Contenido:

Resumen:

Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. In this paper, we: 1) review the perspectives of such devices for low-power high-frequency analog integrated circuit applications (e.g., GHz operation with sub-0.1 mW power consumption), 2) discuss and employ a compact TFET device model in the context of the gm/Id integrated analog circuit design methodology, and 3) compare several proposed TFET technologies for such applications. The advantages of TFETs arise since these devices can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs, which is due to the current turn-on mechanism being interband tunneling rather than thermionic emission. Starting from technology computer-aided design and/or analytical models for Si-FinFETs, graphene nano-ribbon (GNR) TFETs and InAs/GaSb TFETs at the 15-nm gate-length node, as well as InAs double-gate TFETs at the 20-nm gate-length node, we conclude that GNR TFETs might promise larger bandwidths at low-voltage drives due to their high current densities in the sub-threshold region. Based on this analysis and on theoretically predicted properties, GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed-to-date for ultra-low power analog applications.

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IEEE

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Citación:

Barboni, L, Siniscalchi, M, Sensale-Rodriguez, B. "TFET-Based Circuit Design Using the Transconductance Generation Efficiency gm/Id Method," IEEE Journal of the Electron Devices Society, vol. 3, no. 3, pp. 208-216, 2015, doi: 10.1109/JEDS.2015.2412118

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Departamento académico:

Electrónica

Grupo de investigación:

Microelectrónica

Licencia:

Licencia Creative Commons Atribución (CC - By 4.0)
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