| Metadato | Etiqueta | Valor | Idioma |
|---|---|---|---|
| dc.contributor.author | Autor | Barboni, Leonardo | es |
| dc.contributor.author | Autor | Siniscalchi, Mariana | es |
| dc.contributor.author | Autor | Sensale Rodríguez, Berardi | es |
| dc.date.accessioned | Fecha ingreso | 2024-02-26T19:52:47Z | - |
| dc.date.available | Fecha disponible | 2024-02-26T19:52:47Z | - |
| dc.date.issued | Año de publicación | 2015 | es |
| dc.date.submitted | Fecha de subida | 20240223 | es |
| dc.description.abstract | Resumen | Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. In this paper, we: 1) review the perspectives of such devices for low-power high-frequency analog integrated circuit applications (e.g., GHz operation with sub-0.1 mW power consumption), 2) discuss and employ a compact TFET device model in the context of the gm/Id integrated analog circuit design methodology, and 3) compare several proposed TFET technologies for such applications. The advantages of TFETs arise since these devices can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs, which is due to the current turn-on mechanism being interband tunneling rather than thermionic emission. Starting from technology computer-aided design and/or analytical models for Si-FinFETs, graphene nano-ribbon (GNR) TFETs and InAs/GaSb TFETs at the 15-nm gate-length node, as well as InAs double-gate TFETs at the 20-nm gate-length node, we conclude that GNR TFETs might promise larger bandwidths at low-voltage drives due to their high current densities in the sub-threshold region. Based on this analysis and on theoretically predicted properties, GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed-to-date for ultra-low power analog applications. | es |
| dc.identifier.citation | Citación | Barboni, L, Siniscalchi, M, Sensale-Rodriguez, B. "TFET-Based Circuit Design Using the Transconductance Generation Efficiency gm/Id Method," IEEE Journal of the Electron Devices Society, vol. 3, no. 3, pp. 208-216, 2015, doi: 10.1109/JEDS.2015.2412118 | es |
| dc.identifier.doi | DOI | 10.1109/JEDS.2015.2412118 | es |
| dc.identifier.uri | URI | https://hdl.handle.net/20.500.12008/42722 | - |
| dc.language | metadata.dc.language | en | es |
| dc.publisher | Editorial | IEEE | es |
| dc.rights | Derechos | Las obras depositadas en el Repositorio se rigen por la Ordenanza de los Derechos de la Propiedad Intelectual de la Universidad De La República. (Res. Nº 91 de C.D.C. de 8/III/1994 – D.O. 7/IV/1994) y por la Ordenanza del Repositorio Abierto de la Universidad de la República (Res. Nº 16 de C.D.C. de 07/10/2014) | es |
| dc.rights.licence | Licencia | Licencia Creative Commons Atribución (CC - By 4.0) | es |
| dc.subject | Palabras clave | Si-FinFETs | es |
| dc.subject | Palabras clave | Tunnel field effect transistors (TFET) | es |
| dc.subject | Palabras clave | Ultra-low power design | es |
| dc.subject | Palabras clave | gm/Id method | es |
| dc.subject | Palabras clave | One-stage common-source amplifier | es |
| dc.subject | Palabras clave | Two-stage operational transconductance amplifier (OTA) with Miller effect compensation | es |
| dc.subject.other | Descriptores | Electrónica | es |
| dc.title | Título | TFET-Based Circuit Design Using the Transconductance Generation Efficiency gm/Id Method | es |
| dc.type | Tipo de documento | Artículo | es |
| udelar.academic.department | Departamento académico | Electrónica | - |
| udelar.investigation.group | Grupo de investigación | Microelectrónica | - |
Colecciones:
| Ficheros | Descripción | Tamaño | Formato | ||
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| BSS15.pdf | — | 1.06 MB | Adobe PDF |