A 2V rail-to-rail micropower CMOS comparator

Abstract

The design of a rail-to-rail micropower comparator in CMOS technology is described. The circuit is intended for implantable biomedical devices powered by batteries, with a total consumption of 500nA and operation up to supply voltages of 2V. This cell, currently being fabricated, has a core die area of 0.27 mm2 on a 2.4;m standard analog CMOS technology with a 0.85V nominal threshold voltage. It is expected to have a typical response time of 35ms ;and an offset voltage of about 6mV. The limitations imposed by the low supply voltage are presented. The ways of overcoming these limitations, based on an accurate sizing of the transistors for operation in the weak and moderate inversion regions are studied. An approach, based on a capacitive D/A converter, for the generation of a comparison reference input that is digitally programmable is also presented.