Por favor, use este identificador para citar o enlazar este ítem: https://hdl.handle.net/20.500.12008/23855

Título:

Modeling a nanometer FD-SOI transistor with a basic all-region MOSFET model

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Autor:

Siniscalchi, Mariana
Gammarano, Nicolás
Bourdel, Sylvain
Galup Montoro, Carlos
Silveira, Fernando

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Tipo de documento:

Preprint

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Palabras clave:

MOSFET model
FD-SOI
Gm/ID methodology
Weak inversion
Moderate inversion
Table lookup
Capacitance
Parameter extraction
Predictive models

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Año de publicación:

2020

Contenido:

Resumen:

The suitability of a basic, long channel, compact, bulk transistor model coupled with look-up-tables (LUTs) for application to a 28 nm FD-SOI technology is evaluated through simulations. The parameters comprising the LUTs are extracted as a function of the channel length and back-plane voltage, with very simple standard procedures intended for long channel transistors. The resulting model proved to be a simple, but very accurate way to describe the gm/I D curve in the moderate and weak inversion regions, with a straightforward analytical expression, even for minimum length transistors. This approach coupled with a LUT approach for the ID/ gds ratio, provides the main small signal model for design. It was also confirmed that reasonably accurate modeling of the intrinsic capacitances require a more complete modeling of the device.

Descripción:

Presentado y publicado en 2020 IEEE Latin America Electron Devices Conference (LAEDC), San José, Costa Rica, 25-28 feb.

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Citación:

Siniscalchi, M., Gammarano, N., Bourdel, S., y otros. Modeling a nanometer FD-SOI transistor with a basic all-region MOSFET model [Preprint]. Publicado en: IEEE Latin America Electron Devices Conference, San José, Costa Rica, 25-28 feb., 2020. DOI: 10.1109/LAEDC49063.2020.9073239

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Departamento académico:

Electrónica

Grupo de investigación:

Microelectrónica

Licencia:

Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0)
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SGBGS20.pdf Preprint 429.04 KB Adobe PDF