Título:
Efficiency based design flow for fully-integrated class C RF power amplifiers in nanometric CMOS
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Autor:
Barabino, Nicolás
Fiorelli, Rafaella
Silveira, Fernando
Fiorelli, Rafaella
Silveira, Fernando
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Tipo de documento:
Ponencia
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Descriptores:
Electrónica
Año de publicación:
2010
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Resumen:
In this work a design flow for class C radiofrequency (RF) power amplifiers (PA) with on-chip output networks in nanometric technologies is presented. This is a new parasitic-aware method intended to reduce time-consuming iterations which are normally required in fully-integrated designs. Unlike other methods it is based on actual transistors DC characteristics and inductors data both extracted by simulation. Starting from the output power specifications a design space map is generated showing the trade-offs between efficiency and components sizing, thus enabling the selection of the most appropriate design that satisfies the harmonic distortion requirements. As a proof of concept of the proposed method, a design example for an IEEE 802.15.4 2.4 GHz PA in a 90 nm CMOS technology is presented.
Descripción:
Trabajo presentado en IEEE International Symposium on Circuits and Systems
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Citación:
Barabino, N., Fiorelli, R., Silveira, F. Efficiency based design flow for fully-integrated class C RF power amplifiers in nanometric CMOS. [Preprint] Publicado en Proceedings of IEEE International Symposium on Circuits and Systems, Paris, France, 2010. doi 10.1109/ISCAS.2010.5537207.
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Departamento académico:
Electrónica
Electrónica
Electrónica
Grupo de investigación:
Electrónica Aplicada
Microelectrónica
Microelectrónica
Licencia:
Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0)
Colecciones:
| Ficheros | Descripción | Tamaño | Formato | ||
|---|---|---|---|---|---|
| BFS10.pdf | — | 259.21 KB | Adobe PDF |